1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a semiconductor memory device including a fuse array circuit, and an operation method thereof.
2. Description of the Related Art
A semiconductor memory device stores data in a plurality of memory cells that are arranged in a matrix. However, if only a single memory cell has a defect, the semiconductor memory device may malfunction.
As semiconductor memory devices are further integrated and operate faster, the number of defective memory cells may increase. If all semiconductor memory devices with defective memory cells were abandoned as defective products, the production yield of semiconductor memory devices would be deteriorated. To resolve such concern, industry and researchers are developing a semiconductor memory device capable of repairing a defective cell for improving the production yield as well as achieving high integration and faster operating rates.
To repair a defective memory cell, a semiconductor memory device may include redundancy memory cells, for repair, in addition to normal memory cells for performing general read and write operations. When a defect occurs in a normal memory cell among the normal memory cells, the defect may be repaired by substituting the defective memory cell with a redundancy memory cell. To be specific, the address of the normal memory cell, which is detected to have the defect, is stored, and then when the corresponding address is inputted, the redundancy memory cell corresponding to the defective memory cell is accessed.
The defective memory cell of a semiconductor memory device may be detected and repaired in the state of wafer. However, a defect in a semiconductor memory device may occur during the packaging process or burn-in test, which is performed after the packaging process. Thus, a defect in a semiconductor memory device needs to be detected and repaired even after the semiconductor memory device is packaged. This is generally referred to as a post-package repair (PPR) operation.
FIG. 1 is a block view illustrating a conventional semiconductor memory device. Referring to FIG. 1, a post-package repair operation of the conventional semiconductor memory device is described.
The semiconductor memory device 100 includes a program block 110, a repair block 120, a fuse array 130, and a memory cell array 140 including a plurality of memory cells.
The program block 110 may program the fuse array 130 in response to an external command CMD during a program mode. The program block 110 may program address information FADD of a defective memory cell among the memory cells included in the memory cell array 140.
The fuse array 130 includes a plurality of anti-fuses that may be ruptured. The fuse array 130 may program the address information FADD of the defective memory cell by selectively rupturing the anti-fuses. In the wafer stage, information may be programmed by selectively cutting a corresponding fuse with laser beam. The anti-fuses are provided because such operations cannot be performed in the package stage. Anti-fuses generally begin in an open state and may be short-circuited by applying a high voltage to break down the dielectric material within.
When the address information FADD of a defective memory cell is programmed, the repair block 120 compares an inputted address ADD with an address PADD programmed in the fuse array 130, and decides whether to substitute the normal memory cell of the memory cell array 140 corresponding to the inputted address ADD with a redundancy memory cell based on the address comparison result to output the decision result as a signal N/R.
FIG. 2 is a timing diagram for describing an operation of a conventional semiconductor memory device 100 shown in FIG. 1. Referring to FIG. 2, the conventional semiconductor memory device 100 may enter a program mode through a mode register set (MRS) operation, and perform a program operation based on the address inputted along with an active command ACT, in response to a write command WR for data DQ having a predetermined logic level. The program operation may be performed while a program enable signal PGM_EN is activated. That is, the program mode may be defined by an activation period of the program enable signal PGM_EN.
In a conventional semiconductor memory device 100, when a program operation is performed on the fuse array 130 and a refresh operation command REF for the memory cell array 140 is inputted in the middle of the program operation, the refresh operation command REF is ignored and the program operation is performed continuously. This is because when a refresh operation for enabling a plurality of word lines is performed together with the program operation where a fuse is ruptured using high voltage, the currents induced from the operations are added to raise the peak current value. Since high peak current affects both the program operation and the refresh operation, as illustrated in FIG. 2, the refresh operation command REF is disregarded while performing the program operation on the fuse array 130.
However, disregarding of the refresh operation command REF affects how long the memory cells are required to retain data without being refreshed, potentially allowing data in the memory cells to be lost. For example, when 100 refresh operation commands REF are ignored, the data retention time of the cell would be approximately 780 μs. When 1000 refresh operation commands REF are ignored, the data retention time of the cell would be approximately 7.8 ms. Since a program operation of the fuse array 130 may reach hundreds of milliseconds, the increased data retention time of the cell raises the possibility of data loss.